Micro-fabricated device with thermoelectric device and method of making

ABSTRACT

A micro-fabricated device, includes a support structure having an aperture formed therein, and a device substrate disposed within the aperture. The micro-fabricated device further includes a thermally isolating structure thermally coupling the device substrate to the support structure. The thermally isolating structure includes at least one n-doped region and at least one p-doped region formed on or in the thermally isolating structure and separated from each other. In addition, the thermally isolating structure includes an electrical interconnect connecting at least one n-doped region and at least one p-doped region, forming an integrated thermoelectric device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation application and claims the benefitand priority of U. S. patent application Ser. No. 10/353632 filed Jan.29, 2003.

BACKGROUND Description of the Art

Over the past decade, the demand for cheaper and higher performanceelectronic devices has led to a growing need to manufacture electronicdevices having lower power consumption as well as improved thermalefficiency. Microprocessors are a good example of the ever-increasingdemands on power consumption and thus the need to better handle powerdissipation. To a large extent these advances have been made possible byincreases in packaging density which has led to a significant rise inpower dissipation that in turn leads to a substantial increase in chipheat flux. Today's high performance computing devices, if left unalteredwill result in peak temperatures that will destroy or damage thesilicon-based devices on which microprocessors are typically formed.

Demand for improved thermal efficiency is also increasing in theemerging area of Micro-Electro-Mechanical Systems (MEMS), which arebeing developed as smaller alternative systems to conventionalelectromechanical devices such as relays, actuators, sensors, and valvesand other transducers. In addition, such electromechanical devicesincorporated in a MEMS device can be further integrated with integratedcircuits providing improved performance over conventional systems. Manytypes of transducers, incorporated into MEMS devices, such as, vacuumsensors, gas flow sensors, infrared detectors, and AC power convertersoperate in the detection of, or utilization of, a temperature differencethat is isolated from the rest of the integrated circuit (IC).

One methodology utilized in electronics to dissipate heat in asemiconductor device is to provide good thermal conduction between thepackaged semiconductor device and the surrounding outside environment.In many cases, a heat sink attached to the package, which is adapted todissipate heat by relying on convection cooling with air flowing overthe heat sink provided by a fan, is utilized. However, in other casesgood thermal conduction is limited by the opposing need for electricalisolation. That is, in many cases, typically, these two requirements aremutually exclusive because those materials that are good thermalconductors are, also, typically good electrical conductors as well.

In highly integrated systems, such as MEMS devices, different portionsof the same device may operate more efficiently at temperaturessignificantly above or below ambient conditions. For example, a vacuumsensor may operate at its maximum efficiency at over a 100° C. whileassociated CMOS circuitry processing the output of the vacuum sensor orcontrolling some other function may more efficiently operate at roomtemperature or even sub-ambient temperatures such as −25° C. Generally,solutions to such problems results in tradeoffs by utilizing moderatethermal conduction over the device, increasing the power applied to thevacuum sensor to heat it, while also trying to maintain the CMOScircuitry at a lower temperature, typically room temperature. The endresult is an electronic device whose performance is compromised. Theinability to control thermal losses can both, result in a significantincrease in power consumption as well as less than optimum performance.In addition, sub-ambient cooling of electronic devices, such as, forexample, high-end mainframe computer systems, typically, utilizerefrigeration based systems which significantly add to the complexityand cost.

If these problems persist, the continued growth and advancements in theuse electronic devices, especially MEMS devices, in various electronicproducts, seen over the past several decades, will be reduced. In areaslike consumer electronics, the demand for cheaper, smaller, morereliable, higher performance electronics constantly puts pressure onimproving and optimizing performance of ever more complex integrateddevices. The ability, to optimize thermal performance will open up awide variety of applications that are currently either impractical ornot cost effective.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 a is a top view of a micro-fabricated device according to anembodiment of the present invention;

FIG. 1 b is a cross-sectional view of the micro-fabricated device shownin FIG. 1 a according to an embodiment of the present invention;

FIG. 1 c is a cross-sectional view of the micro-fabricated device shownin FIG. 1 a according to an embodiment of the present invention;

FIG. 1 d a cross-sectional view of the micro-fabricated device shown inFIG. 1 a according to an alternate embodiment of the present invention;

FIG. 2 is a top view of a micro-fabricated device according to analternate embodiment of the present invention;

FIG. 3 a is a top view of a micro-fabricated device according to analternate embodiment of the present invention;

FIG. 3 b is a cross-sectional view of the micro-fabricated device shownin FIG. 3 a according to an alternate embodiment of the presentinvention;

FIG. 4 a is a top view of a micro-fabricated device according to analternate embodiment of the present invention;

FIG. 4 b is a cross-sectional view of the micro-fabricated device shownin FIG. 4 a according to an alternate embodiment of the presentinvention;

FIG. 4 c is a cross-sectional view of the micro-fabricated device shownin FIG. 4 a according to an alternate embodiment of the presentinvention;

FIG. 4 d is a cross-sectional view of the micro-fabricated device shownin FIG. 4 a according to an alternate embodiment of the presentinvention;

FIG. 5 is a cross-sectional view of a micro-fabricated device having anintegrated vacuum device according to an alternate embodiment of thepresent invention;

FIG. 6 is a block diagram of an electronic device according to anembodiment of the present invention;

FIG. 7 is a flow chart of a method of making a micro-fabricated deviceaccording to an embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1 a, a top view is shown of an embodiment ofmicro-fabricated device 100 of the present invention. In thisembodiment, thermally isolating structure 120 includes thermoelectricdevice 150 that provides selective heating or cooling of devicesubstrate 130. In addition, thermally isolating structure 120 reducesthe thermal conductivity between device substrate 130 and supportstructure 140 while also providing mechanical support. Device substrate130 is disposed, within aperture 142 formed in support structure 140.

In this embodiment, active device 134 is disposed on device substrate130. Active device 134 includes, for example, various transistors(including thin-film-transistor (TFT) technology using polysilicon onglass substrates), diodes, logic cells, as well as sensors, transducers,electron emitters, bolometers, and superconductoring high Q RF filtersto name just a few of the many active devices that may be utilized inthe present invention either separately or in combination. To simplifythe drawing active device 134 is represented as only a single layer inFIGS. 1 a-1 c although it is readily apparent that such devicestypically may be realized as a stack of thin film layers.

It should be noted that the drawings are not true to scale. Further,various elements have not been drawn to scale. Certain dimensions havebeen exaggerated in relation to other dimensions in order to provide aclearer illustration and understanding of the present invention.

In addition, although some of the embodiments illustrated herein areshown in two dimensional views with various regions having depth andwidth, it should be clearly understood that these regions areillustrations of only a portion of a device that is actually a threedimensional structure. Accordingly, these regions will have threedimensions, including length, width, and depth, when fabricated on anactual device. Moreover, while the present invention is illustrated byvarious embodiments, it is not intended that these illustrations be alimitation on the scope or applicability of the present invention.Further it is not intended that the embodiments of the present inventionbe limited to the physical structures illustrated. These structures areincluded to demonstrate the utility and application of the presentinvention to presently preferred embodiments.

Thermoelectric device 150 is formed utilizing a plurality of n-dopedregions 152 and p-doped regions 154 formed in thermally isolatingstructure 120. N-doped regions 152 and p-doped regions 154 are formed byselectively implanting the desired dopant in the desired area as shownin cross-sectional view in FIG. 1 b and 1 c. In this embodiment, then-doped and p-doped regions are square in shape; however, in alternateembodiments, other shapes such as a rectangle may also be utilized. Theparticular shape utilized will depend on, for example, the desiredheating or cooling characteristics of thermoelectric device 150, theshape of thermally isolating structure 120, and the particular materialused to form thermally isolating structure 120. In addition, both thedopant level and depth may also be varied. The doped regions are formedutilizing conventional photolithographic and implanting equipment, suchas ion beam implantation through a dielectric layer opening, or a masklayer generated photo lithographically. The doped regions are arrangedand electrically coupled to each other in such a manner that theelectronic carriers, i.e. holes and electrons in p-doped regions 154 andn-doped regions 152 respectively, work cooperatively to heat or cooldevice substrate 130.

The n-doped and p-doped regions are electrically connected by couplingconductors 156, and end portion 158′ of segment conductors 158, overn-doped and p-doped regions 152 and 154, generating an alternatingseries as shown, in cross-sectional view, in FIG. 1 c. Couplingconductors 156, and segment conductors 158, are thin films deposited,for example, by sputter deposition through the desired pattern openingsgenerated utilizing photolithographic processes and associated etchprocesses. In this embodiment, coupling conductors 156 and segmentconductors 158 are aluminum conductors, however, in alternateembodiments, any electrical conductor having the desired currentcarrying capacity may also be utilized, such as for example, gold,tungsten, copper, and platinum to name a few. During operation currentis applied to thermoelectric device 150 through either power conductor160 or 161. For example, current applied to power conductor 161connected to an n-doped region and returned through power conductor 160connected to a p-doped region causes the majority carriers to travel inthe same direction so that thermal energy (i.e. the majority carriersare also the majority thermal carriers) is transferred from devicesubstrate 130 to support structure 140 through thermally isolatingstructure 120 thereby cooling device substrate 130. If the current isreversed then the direction of travel of the majority carriers isreversed and the direction of thermal transfer is also reversed so thatthermal energy is transferred from support 140 to device substrate 130thereby heating device substrate 130.

Device substrate 130, thermally isolating structures 120, and supportstructure 142 form a substantially planar structure as shown incross-sectional views in FIGS. 1 b and 1 c. In this embodiment, devicesubstrate 130, support structure 140 and thermally isolating structures120 are formed from an intrinsic silicon wafer. In alternateembodiments, silicon on insulator, lightly doped semiconductor wafers,epitaxial silicon grown over an oxide may also be utilized. In stillother embodiments, micro-fabricated device 100 may be formed utilizingwafers or substrates made from materials such as glass, sapphire,ceramic, gallium arsenide, germanium, indium phosphide, and variouspolymers to name just a few. The particular material utilized formicro-fabricated device 100 will depend on various parameters, such as,the particular application in which the device will be utilized, bothprocess and operating temperatures, the presence or absence of activeelectronic devices, and the thermal and mechanical properties of thedevice. In addition, cross-sectional area 115 of thermally isolatingstructures 120 may vary to further tune the thermal conduction ofisolating structures 120 by varying the thickness of thermally isolatingstructure 120. For example, cross-sectional area 115 of thermallyisolating structures 120 has a uniform thickness as shown in FIGS. 1 a-1c. In alternate embodiments, the cross-sectional area may vary over thelength of thermally isolating structure 120 as shown in FIG. 1 d, wherecross-sectional area 115′ near device substrate 130 is less than thecross-sectional area 115″ near substrate 140.

Referring to FIG. 2, an alternate embodiment of thermoelectric device250 is shown in a top view. Thermally isolating structure 220 has atrapezoidal shape providing thermoelectric device 250 with an increasingnumber of pn pairs or thermoelectric segments. The particular number ofpn pairs or thermoelectric segments will depend on the particularapplication in which the micro-fabricated device will be utilized. Inthis embodiment, thermally isolating structure 220 has one pair atperipheral edge 232 of device substrate 230, and increasing to fourpairs at inner edge 244 of support structure 240. Such a structurereduces the thermal conduction out of device substrate 230 and increasesthe thermal energy transferred to support structure 240 by theincreasing number of thermoelectric elements. Although only onethermally isolating structure 220 is shown for illustrative purposes, inthis embodiment, multiple structures may be utilized to optimize thethermal energy transfer between device substrate 230 and supportstructure 240. For example, four isolating structures each having athermoelectric device, one isolating structure attached to eachperipheral side of a device substrate having four sides may be utilized,or multiple isolating structures attached to each peripheral side (e.g.2, 3, 4 or more) may also be utilized. Another example, suitable for acircular shaped device substrate would have multiple structuresemanating in a radial direction from the peripheral edge of the devicesubstrate. In addition, device substrate 230 may also utilize variousactive devices (not shown) as described earlier.

Referring to FIG. 3 a, an alternate embodiment of micro-fabricateddevice 300 of the present invention is shown in a top view. In thisembodiment, thermally isolating structure 320 includes, thermoelectricdevices 350, and reduces the thermal conduction between device substrate330 and support structure 340. Thermally isolating structure 320 hascharacteristic length or thermal conduction path 318 measured betweenpoints 321, where path 318 is greater than distance G the gap betweensupport structure 340 and device substrate 330 formed by aperture 342.The longer thermal conduction path of thermally isolating structure 320reduces the thermal conduction between device substrate 330 and supportstructure 340 compared to a straight structure having length G and asimilar cross-sectional area as thermally isolating structure 320.

In this embodiment, thermally isolating structure 320 includes a foldedstructure having at least one fold. Thermally isolating structure 320includes first section 364, second section 366 and folding section 368.First section 364 and second section 366 are substantially parallel toeach other with the three sections 364, 366, and 368 forming a U shapedstructure. In addition thermally isolating structure 320 also providesmechanical support of device substrate 330. Device substrate 330 isdisposed, within aperture 342 formed in support structure 340.

Thermoelectric device 350 is formed utilizing a plurality of n-dopedregions 352 and p-doped regions 354 formed in thermally isolatingstructure 320. In this embodiment, the n-doped and p-doped regions areslightly offset to provide space for segment conductor 358. However, inan alternate embodiment, segment conductors may also be routed over adoped region to further reduce the width, and thus cross-sectional area315, of thermally isolating structure 320. A dielectric layer such assilicon oxide or nitride or polymer dielectric is, in this case,interposed between the doped region and segment conductor 358 to provideelectrical isolation. In this embodiment, coupling conductors 356 andsegment conductors 358 may be any electrical conductor having thedesired current carrying capacity as described earlier. Current isapplied to either power conductor 360 or 361 depending on whethersubstrate 330 is heated or cooled. In addition, cross-sectional area 315of thermally isolating structures 320 may vary to further tune thethermal conduction of isolating structures 320 by varying the thicknessof thermally isolating structure 320.

Referring to FIG. 4 a, a top view of micro-fabricated device 400, analternate embodiment of the present invention, is shown. In thisembodiment, peltier or thermoelectric device 450 includes segmentsformed on both first major or top surface 422 and second major or bottomsurface 424 (see FIG. 4 b-4 d) of thermally isolating structure 420 thatis attached to peripheral edge 432 of device substrate 430 and inneredge 444 of support structure 440. In addition, thermally isolatingstructure 420 has characteristic length 418 measured between points 421,where characteristic length or thermal conduction path 418 is greaterthan distance G the gap between support structure 440 and devicesubstrate 430 formed by aperture 442. In this embodiment, characteristiclength 418 is representative of the thermal path, that thermal energytravels between device substrate 430 and support structure 440.

Device substrate 430 is disposed, within aperture 442 formed in supportstructure 440. Active device 434 is disposed on device substrate 430.Active device 434 includes any of the various active devices describedin previous embodiments. In this embodiment, device substrate 430,thermally isolating structure 420, and support structure may be formedfrom any material on which active device 434 may be formed.

Peltier device 450 includes n-doped region 452 and p-doped region 454formed on major surface 422 and n-doped region 452′ and p-doped region454′ on second major surface 424 as shown, in a cross-sectional view, inFIGS. 4 c-4 d. In this embodiment, device substrate 430 and thermallyisolating structure 420 utilize an electrically insulating substratesuch as a glass or polymer substrate. The n and p doped regions may beformed by deposition of a high Seebeck coefficient material such asSbTe, BiTe, PbTe, and various skutterdites including ternaryskutterdites, to name just a few examples, on thermally isolatingstructure 420. The high Seebeck coefficient material may be deposited bysputter deposition, plasma enhanced chemical vapor deposition,evaporation, or other appropriate deposition process. For thoseembodiments utilizing a semiconductor wafer to form device substrate 430and thermally isolating structure 420 the n and p doped regions may beformed either by deposition of the high Seebeck coefficient material orby ion implantation as described above in previous embodiments or somecombination thereof, utilizing the appropriate electrical interconnectand isolation scheme. In this embodiment, each leg of thermallyisolating structure 420 forms either an n-doped or p-doped region,however, in alternate embodiments multiple n and p-doped regions mayalso be utilized. Coupling conductors 456 and 456′ electrically couplen-doped regions to p-doped regions as shown in FIGS. 4 a and 4 b. Powerconductors 460, and 461, through which current is applied to peltierdevice 450, are electrically coupled to one end of the p and n dopedregions. In this embodiment, current is applied to both segments viapower conductors 460 and 461 as shown in FIG. 4 a. Via conductor 426provides an electrical path between power conductor 460 and 460′ and viaconductor 428 provides an electrical path between conductor 461 and 461′as shown in cross-sectional view in FIG. 4 d, thereby providingelectrical power to the bottom or lower segment. In alternateembodiments, current may be applied to power conductors 460′ and 461′separately by, for example, utilizing electrical traces formed androuted on the bottom or underside surface of support structure 440.

FIG. 5 is an exemplary embodiment of a micro-fabricated device havingintegrated vacuum device 502 that includes anode surface 568 such as adisplay screen or a mass storage device that is affected by electrons562 when they are formed into a focused beam 564. Thermally insulatingstructure 520 includes thermoelectric device 550 that provides heatingor cooling of device substrate 530 depending on the particularperformance parameters desired to be optimized. In addition, thermallyinsulating structure 520 also reduces the thermal conduction betweendevice substrate 530 and support structure 540 while providingmechanical support. Device substrate 530 is disposed, within aperture542 formed in support structure 540. Anode surface 568 is held at apredetermined distance from second electron lens element 552.Micro-fabricated device 500 is enclosed in a vacuum package (not shown).

In this embodiment, integrated vacuum device 502 is shown in asimplified block form and may be any of the electron emitter structureswell known in the art such as a Spindt tip or flat emitter structure.Second lens element 552 acts as a ground shield. Vacuum device 502 isdisposed over at least a portion of device substrate 530. Firstinsulating or dielectric layer 554 electrically isolates second lenselement 552 from first lens element 556. Second insulating layer 558electrically isolates first lens element 556 from vacuum device 502 andsubstrate 530. In alternate embodiments, more than two lens elements,may also be utilized to provide, for example, an increased intensity ofemitted electrons 562, or an increased focusing of electron beam 564, orboth. Utilizing conventional semiconductor processing equipment both thelens elements and dielectrics may be fabricated.

As a display screen, an array of pixels (not shown) are formed on anodesurface 568, which are typically arranged in a red, blue, green order,however, the array of pixels may also be a monochromatic color. An arrayof emitters (not shown) are formed on device substrate 530 where eachelement of the emitter array has one or more integrated vacuum devicesacting as an electron emitter. Application of the appropriate signals toan electron lens structure including first and second electron lenselements 552 and 556 generates the necessary field gradient to focuselectrons 562 emitted from vacuum device 502 and generate focused beam564 on anode surface 568.

As a mass storage device, anode surface 568 typically includes aphase-change material or storage medium that is affected by the energyof focused beam 564. The phase-change material generally is able tochange from a crystalline to an amorphous state (not shown) by using ahigh power level of focused beam 564 and rapidly decreasing the powerlevel of focused beam 564. The phase-change material is able to changefrom an amorphous state to a crystalline state (not shown) by using ahigh power level of focused beam 564 and slowly decreasing the powerlevel so that the media surface has time to anneal to the crystallinestate. This change in phase is utilized to form a storage area on anodesurface 568 that may be in one of a plurality of states depending on thepower level used of focused beam 564. These different states representinformation stored in that storage area.

An exemplary material for the phase change media is germanium telluride(GeTe) and ternary alloys based on GeTe. The mass storage device alsocontains electronic circuitry (not shown) to move anode surface 568 in afirst and preferably second direction relative to focused beam 564 toallow a single integrated vacuum device 502 to read and write multiplelocations on anode surface 568. To read the data stored on anode ormedia surface 568, a lower-energy focused beam 564 strikes media surface568 that causes electrons to flow through the media substrate 560 and areader circuit (not shown) detects them. The amount of current detectedis dependent on the state, amorphous or crystalline, of the mediasurface struck by focused beam 564.

Referring to FIG. 6 an exemplary block diagram of an electronic device608, such as a computer system, video game, Internet appliance,terminal, MP3 player, cellular phone, or personal digital assistant toname just a few. Electronic device 608 includes microprocessor 670, suchas an Intel processor sold under the name “Pentium Processor,” orcompatible processor. Many other processors exist and may also beutilized. Microprocessor 670 is electrically coupled to a memory device668 that includes processor readable memory that is capable of holdingcomputer executable commands or instructions used by the microprocessor670 to control data, input/output functions, or both. Memory device 668may also store data that is manipulated by microprocessor 670.Microprocessor 670 is also electrically coupled either to storage device604, or display device 606 or both. Microprocessor 670, memory device668, storage device 604, and display device 606 each may contain anembodiment of the present invention as exemplified in earlier describedfigures and text showing device substrates having thermally isolatingstructures.

Referring to FIG. 7 a flow diagram of a method of manufacturing amicro-fabricated device, according to an embodiment of the presentinvention, is shown. Substrate creating process 780 is utilized tocreate or form the substrate in which the device substrate and supportstructure may be created. The substrate is a single crystal intrinsicsilicon wafer having a thickness of about 200-800 microns. However, inalternate embodiments, both other materials and thicknesses may beutilized. For example, silicon on insulator, lightly n or p dopedsilicon wafers, gallium arsenide, and indium phosphide are just a few ofother semiconductor wafer technologies that may also be utilized.Further, in still other embodiments, glass, ceramic, and polymersubstrates are just a few of the alternate materials that may also beused in the present invention. Thus, substrate creating process 780 isnot restricted to typical wafer sizes, and may include processing apolymer sheet or film or glass sheet or even a single crystal sheet orsubstrate handled in a different form and size than that of conventionalsilicon wafers.

Dopant region creation process 782 is utilized to create the n-doped andp-doped regions utilized to form the thermal transfer segments of thethermoelectric device formed on the thermally isolating structure of thepresent invention. In addition dopant region creation process 782 mayalso be utilized to create n-doped and p-doped regions for other activeelectronic devices described earlier, and will depend on the particulardevices utilized as well as the particular application in which themicro-fabricated device will be utilized. The doped regions aregenerally formed sequentially. A silicon oxide or nitride or othersuitable material is deposited over the substrate and patterned to forma mask having openings of the desired shape of the doped region. Theparticular dopant is then generally implanted, to the desired dose, intothe open region of the mask utilizing conventional ion implantationequipment; however, other implantation processes may also be utilized.An annealing step generally follows the dopant implantation process. Theparticular annealing process is ion-dose and ion-species-dependent. Themask is then removed generally by chemical etching, however, anysuitable etching process or layer removable process may be utilized. Theprocess is then repeated for the complementary dopant to form then-doped and p-doped regions.

Device structure creation process 784 is utilized to create MEMSstructures or active devices or combinations of both on themicro-fabricated device. Depending on the particular application inwhich micro-fabricated device will be utilized any MEMS structure may becreated, for example, MEMS structures may include transducers,actuators, sensors, and valves to name a few. In addition, devicestructure creation process 784 also includes creating various electroniccircuits such as, for example, transistors, logic circuits, memorycells, as well as, passive devices such as capacitors, resistors, andinductors. For clarity these devices are represented as a single layerin the various embodiments shown. The particular devices and circuitscreated will depend on the particular application in which themicro-fabricated device will be utilized. Typically, the electroniccircuits are fabricated utilizing conventional IC processing equipmentand processes generally involving deposition, patterning, and etchingprocesses. Bulk or surface micromachining or combinations of both mayalso be utilized to form the MEMS structures. For example, an integratedpressure sensor is typically fabricated using IC processing to createthe driving and analysis circuits followed by micromachining from thebackside of the wafer to create a micromachined diaphragm. Otherexamples, include infrared sensing arrays formed utilizing IC processingto form thermopiles and other circuitry followed by micromachining tocreate the sensing array, or fabricating an amplifier operating in theradio frequency range utilizing CMOS technology to fabricate the ICamplifier and micromachining to produce an inductor with the properresonance frequency. In an alternate embodiment, device structurecreation process 784 may also utilize LIGA (a German acronymlithographe, galvanoformung, abformung), a technique for fabrication ofthree-dimensional structures with high aspect ratios involvinglithography, electroforming, and micromolding. Device structure creationprocess 784 also includes deposition and pattern generation forelectrical traces and interconnect pads providing for the routing ofsignals and power to various portions of the micro-fabricated device.

Conductor creation process 786 is utilized to form the couplingconductors, segment conductor, and power conductors for thethermoelectric device. The conductors are electrically conductive andmay be metal or alloy thin films; however, any electrical conductorhaving the desired current carrying capacity may be utilized. Variousdeposition techniques such as sputter deposition, chemical vapordeposition, evaporation, electrodeposition, or other vapor depositiontechnique may be utilized to create the conductors. The particulardeposition technique utilized will depend on the particular materialchosen for the electrical conductors. Examples of typical metals thatmay be utilized are aluminum, gold, tungsten, copper, tantalum, andplatinum to name a few. Photolithography and associated etches processesare used to generate the desired pattern of the coupling, segment, andpower conductors.

Thermally isolating structure creation process 788 is utilized to createthe thermally isolating structures. A dielectric passivation layer isdeposited over the silicon substrate, MEMS and electronic devices. Thedielectric layer may be deposited utilizing deposition techniques suchas plasma enhanced chemical vapor deposition (PECVD), atmospheric or lowpressure chemical vapor deposition, sputter deposition, or othersuitable deposition technique may be utilized to deposit refractorydielectrics such as silicon oxide, silicon nitride, or silicon carbideto name just a few examples. In alternate embodiments, spin coating,curtain coating, or screen printing may also be utilized to form apolymer dielectric passivation layer such as polyimides, orbenzocyclobutene as just a couple of examples. After deposition variousplanarizing processes such as chemical mechanical processing (CMP) maybe utilized for those applications desiring a planarized dielectriclayer. An etch defining layer is deposited on the back or opposite sideof the silicon substrate. Generally the etch defining layer is a siliconnitride or oxide layer, however, in alternate embodiments, otherrefractory materials such as silicon carbide or an oxynitride film mayalso be used. In still other embodiments polymeric materials such as aphoto resist or polyimide may also be utilized depending on variousparameters such as the particular substrate material utilized as well asthe particular etchant utilized to form the thermally isolatingstructures. The etch defining layer is then patterned in the desiredshape to form the thermally isolating structures, the device substrate,and the support structure utilizing conventional photolithographictechnologies and processes leaving those areas, such as the aperture orgap between the device substrate and support structure, to be etchedopened. The size and shape of these openings also depends on variousparameters such as particular etchant utilized as well as the substratematerial. For example, an anisotropic wet etch such as potassiumhydroxide (KOH) or tetra methyl ammonium hydroxide (TMAH), may beutilized to etch a (100) oriented silicon wafer, and produce variousstructures with sloped side walls generated by the slower etch rate ofthe (111) crystallographic planes. Alternatively a dry etch may be usedwhen vertical or orthogonal sidewalls are desired. In addition,combinations of wet and dry etch may also be utilized when more complexstructures are desired. Further, other processes such as laser ablation,reactive ion etching, ion milling including focused ion beam patterningmay also be utilized to form the thermally isolating structures, thedevice substrate, and the support structure. After the thermallyisolating structures are formed the dielectric passivation layer and theetch defining layer may be completely removed or left in selectiveareas, depending on various parameters such as the desired thermal andelectrical isolation properties of various portions of themicro-fabricated device as well as the particular type of packageutilized.

Package forming process 790 is utilized to enclose the micro-fabricateddevice providing protection from physical damage, as well as,contamination and environmental degradation. The particular packageutilized will depend on various parameters such as cost, deviceperformance, and reliability. For example, for those microfabricateddevices utilizing a vacuum package package bond structures may be formedon the support structure over the dielectric passivation layer and theetch defining layer, which provide electrical isolation. The packagebond structures, for example, may be a gold-silicon eutectic for bondinga silicon die to a ceramic package or metal can or the bond structuresmay be a softer lower melting point solder to illustrate a couple ofexamples of materials that may be utilized.

Generally the package consists of a lid or a cover and a base. Bondstructures are also formed on the lid and base. The material utilizedfor the package bond structures, as well as, the lid and base bondstructures will depend on the particular materials utilized for thedevice substrate, support structure and the base and lid. The base andlid may be formed from various, ceramic, glass, or metal materials. Theparticular material will depend on, for example, the desired pressure tobe maintained; the temperature and humidity and other environmentalfactors to which the micro-fabricated device will be exposed; and theamount of stress that may be imparted to the micro-fabricated device asa result of the packaging process; as well as, the particular sealingtechnology to be utilized. These same parameters are also consideredwhen determining what material to be utilized as bond structures. Theseal can be made by a variety of techniques including thermalcompression, brazing, anodic bonding, as well as other techniques.

1. A micro-fabricated device, comprising a support structure including an aperture formed therein; a device substrate disposed at least partially within said aperture; and a thermally isolating structure coupling said device substrate to said support structure; and at least one thermoelectric segment integrated on or at a first major surface of said thermally isolating structure.
 2. The micro-fabricated device in accordance with claim 1, wherein said device substrate further comprises a peripheral edge, wherein said support structure further comprises an inner edge, wherein said peripheral edge is disposed a distance G from said inner edge, said distance G being measured proximate to said thermally isolating structure, and wherein said thermally isolating structure further comprises a thermally isolating structure length that is the thermal conduction path length thermal energy travels between said device substrate and said support structure, wherein said thermally isolating structure length is greater than said distance G.
 3. The micro-fabricated device in accordance with claim 1, wherein said at least one thermoelectric segment further comprises a plurality of thermoelectric segments, wherein said device substrate further comprises a peripheral edge, wherein said support structure further comprises an inner edge, wherein the number of thermoelectric segments increases in the direction from said peripheral edge to said inner edge.
 4. The micro-fabricated device in accordance with claim 1, wherein said thermally isolating structure further comprises a folded structure having at least one fold.
 5. The micro-fabricated device in accordance with claim 1, wherein said thermally isolating structure further comprises a thickness less than the thickness of said device structure.
 6. The micro-fabricated device in accordance with claim 1, wherein said thermally isolating structure further comprises a cross-sectional area that varies.
 7. The micro-fabricated device in accordance with claim 1, wherein said thermally isolating structure further comprises a structure projecting in a radial direction from a peripheral edge of said device substrate.
 8. The micro-fabricated device in accordance with claim 1, further comprising at least one active device disposed on said device substrate.
 9. The micro-fabricated device in accordance with claim 8, wherein said at least one active device further comprises at least one transistor.
 10. The micro-fabricated device in accordance with claim 1, further comprising a vacuum device disposed on said device substrate.
 11. The micro-fabricated device in accordance with claim 10, wherein said vacuum device further comprises an electron emitter.
 12. A storage device, comprising: at least one micro-fabricated device of claim 11; and a storage medium in close proximity to said at least one electronic device, said storage medium having a storage area in one of a plurality of states to represent information stored in that storage area.
 13. A computer system, comprising: a microprocessor; an electronic device including at least one micro-fabricated device of claim 1 coupled to said microprocessor; and memory coupled to said microprocessor, said microprocessor operable of executing instructions from said memory to transfer data between said memory and the electronic device.
 14. The computer system in accordance with claim 13, wherein said electronic device is a storage device.
 15. The computer system in accordance with claim 13, wherein said electronic device is a display device.
 16. The computer system in accordance with claim 13, wherein said microprocessor further comprises a micro-fabricated device having: a support structure including an aperture formed therein; a device substrate disposed within said aperture; and a thermally isolating structure thermally coupling said device substrate to said support structure, said thermally isolating structure comprising: at least one n-doped region disposed on or in said thermally isolating structure, at least one p-doped region disposed on or in said thermally isolating structure, and an electrical interconnect connecting said at least one n-doped region and said at least one p-doped region, whereby an integrated thermoelectric device is formed.
 17. The micro-fabricated device in accordance with claim 1, wherein said thermally isolating structure further comprises a second major surface, wherein at least one thermoelectric segment is disposed on or in said thermally isolating structure at each of said first and second major surfaces.
 18. The micro-fabricated device in accordance with claim 1, wherein said at least one thermoelectric segment further comprises at least one n-doped or p-doped region that includes a high Seebeck coefficient material.
 19. A micro-fabricated device, comprising: a device substrate disposed at least partially within an aperture formed in a support structure; means for hindering thermal conduction disposed between said device substrate and said support structure; and means for thermoelectrically heating and/or cooling integrally disposed on or at a surface of said means for hindering thermal conduction.
 20. A micro-fabricated device, comprising a support structure including an aperture formed therein; a device substrate disposed at least partially within said aperture; a thermally isolating structure integrally coupling said device substrate to said support structure; and a thermoelectric device integrally disposed on or at a first major surface of said thermally isolating structure.
 21. A micro-fabricated device, comprising a support structure including an aperture formed therein; a device substrate disposed at least partially within said aperture; and a thermally isolating structure coupling said device substrate to said support structure, said thermally isolating structure having: at least one n-doped region disposed on or in said thermally isolating structure, at least one p-doped region disposed on or in said thermally isolating structure, and an electrical interconnect connecting said at least one n-doped region and said at least one p-doped region, forming at least one thermoelectric segment integrated with said thermally isolating structure. 